Clock signals are used for timing or synchronizing operations within many electronic devices. For example, clock signals are used for timing or synchronizing read and write operations for memories, such as flash memories, dynamic random access memories (DRAMs), static random access memories (SRAMs), etc., of electronic devices, such as desktop or portable computers. For some applications, clock signals are used to control data latching for read and write applications. For one application, such as for double-data-rate DRAMs, it is advantageous to latch data, for example, every half-clock cycle. This typically involves using a first latch of a latch system to latch data when the clock signal goes from low to high, i.e., on a positive clock transition (or positive clock edge), and using a second latch of the latch system to latch data a half clock cycle later when the clock signal goes from high to low, i.e., on a negative clock transition (or negative clock edge).
Typically, latches that latch data on positive clock transitions are of a different type than latches that latch data on negative clock transitions. For example, latches that latch data on positive clock transitions are often p-channel devices, whereas latches that latch data on negative clock transitions are often n-channel devices. One problem with this is that different type latches can cause timing variations that can distort the data output of the latch system. Therefore, it is often advantageous to latch data on a single clock edge, either positive or negative. Four-phase clocks can used to generate positive or negative clock edges at half clock cycle intervals. Each clock phase is then used to control a latch of a latch system having common latch types.
One method of developing a four-phase clock is to use each phase of a two phase-clock to drive two clock dividers. The clock dividers are then started in sequence at half clock cycle intervals. This often involves aligning a first phase of the two-phase clock with a second phase of the two-phase clock so that the first and second phases are a half clock cycle out of phase. That is, so that the first clock phase transitions high when the second clock phase transitions low and vice versa. Then, a first divider is started from a reset state when the first phase of the two-phase clock transitions high to start the first phase of the four-phase clock. A half clock cycle later, a second divider is started from a reset state when the second phase of the two-phase clock transitions high to start the second phase of the four-phase clock. Another half clock cycle later, a third divider is started from a reset state when the first phase of the two-phase clock transitions high again to start the third phase of the four-phase clock. Another half-clock cycle later, a fourth divider is started from a reset state when the second phase of the two-phase clock transitions high again to start the fourth phase of the four-phase clock. However, for relatively high frequencies, the half cycle intervals do not provide enough time to start the dividers owing to logic delays and startup times for the dividers.
For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for alternatives for starting phases of multiphase clocks.